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Espressif Systems /ESP32-S2 /UART0 /CONF0

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Interpret as CONF0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PARITY)PARITY 0 (PARITY_EN)PARITY_EN 0BIT_NUM 0STOP_BIT_NUM 0 (SW_RTS)SW_RTS 0 (SW_DTR)SW_DTR 0 (TXD_BRK)TXD_BRK 0 (IRDA_DPLX)IRDA_DPLX 0 (IRDA_TX_EN)IRDA_TX_EN 0 (IRDA_WCTL)IRDA_WCTL 0 (IRDA_TX_INV)IRDA_TX_INV 0 (IRDA_RX_INV)IRDA_RX_INV 0 (LOOPBACK)LOOPBACK 0 (TX_FLOW_EN)TX_FLOW_EN 0 (IRDA_EN)IRDA_EN 0 (RXFIFO_RST)RXFIFO_RST 0 (TXFIFO_RST)TXFIFO_RST 0 (RXD_INV)RXD_INV 0 (CTS_INV)CTS_INV 0 (DSR_INV)DSR_INV 0 (TXD_INV)TXD_INV 0 (RTS_INV)RTS_INV 0 (DTR_INV)DTR_INV 0 (CLK_EN)CLK_EN 0 (ERR_WR_MASK)ERR_WR_MASK 0 (TICK_REF_ALWAYS_ON)TICK_REF_ALWAYS_ON 0 (MEM_CLK_EN)MEM_CLK_EN

Description

Configuration register 0

Fields

PARITY

This register is used to configure the parity check mode. 0: even. 1: odd.
PARITY_EN

Set this bit to enable UART parity check.
BIT_NUM

This register is used to set the length of data. 0: 5 bits. 1: 6 bits. 2: 7 bits. 3: 8 bits.
STOP_BIT_NUM

This register is used to set the length of stop bit. 1: 1 bit. 2: 1.5 bits. 3: 2 bits.
SW_RTS

This register is used to configure the software RTS signal which is used in software flow control.
SW_DTR

This register is used to configure the software DTR signal which is used in software flow control.
TXD_BRK

Set this bit to enable the transmitter to send NULL characters when the process of sending data is done.
IRDA_DPLX

Set this bit to enable IrDA loopback mode.
IRDA_TX_EN

This is the start enable bit for IrDA transmitter.
IRDA_WCTL

1: The IrDA transmitter’s 11th bit is the same as 10th bit. 0: Set IrDA transmitter’s 11th bit to 0.
IRDA_TX_INV

Set this bit to invert the level of IrDA transmitter.
IRDA_RX_INV

Set this bit to invert the level of IrDA receiver.
LOOPBACK

Set this bit to enable UART loopback test mode.
TX_FLOW_EN

Set this bit to enable flow control function for the transmitter.
IRDA_EN

Set this bit to enable IrDA protocol.
RXFIFO_RST

Set this bit to reset the UART RX FIFO.
TXFIFO_RST

Set this bit to reset the UART TX FIFO.
RXD_INV

Set this bit to invert the level of UART RXD signal.
CTS_INV

Set this bit to invert the level of UART CTS signal.
DSR_INV

Set this bit to invert the level of UART DSR signal.
TXD_INV

Set this bit to invert the level of UART TXD signal.
RTS_INV

Set this bit to invert the level of UART RTS signal.
DTR_INV

Set this bit to invert the level of UART DTR signal.
CLK_EN

1: Force clock on for registers. 0: Support clock only when application writes registers.
ERR_WR_MASK

1: The receiver stops storing data into FIFO when data is wrong. 0: The receiver stores the data even if the received data is wrong.
TICK_REF_ALWAYS_ON

This register is used to select the clock. 1: APB_CLK. 0: REF_TICK.
MEM_CLK_EN

The signal to enable UART RAM clock gating. 1: UART RAM powers on, the data of which can be read and written. 0: UART RAM powers down.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data